empro.toolkit.analysis.regression

9 # mode: 0 = run analyses, 1 = generate test bench, 2 = run circuit simulation, 3 = generate schematic and compare (no simulation)

10 - def __init__(self, mode, aelFunctionName='', **kwargs):

11 self.mode = mode 12 self.aelFunctionName = aelFunctionName 13 self._processKWargs(**kwargs) 14 self.datasetNames = [] 15 self.failedAnalyses = [] 16 self.timeOuts = [] 17 self.totalSimTime = 0 18 self.pprFileNames = [] 19 self.schemGenResults = []

20

21 - def _processKWargs(self, **kwargs):

22 self.timeout = None 23 if "timeout" in kwargs: 24 try: 25 self.timeout = int(kwargs["timeout"]) 26 except TypeError: 27 self.timeout = None

28

29 - def callAel(self):

30 if len(self.aelFunctionName) == 0: 31 return 32 33 import empro.core, empro.toolkit.rpc 34 if not empro.core.CommunicationWithParent.wasActivated(): 35 raise Exception('Communication with ADS is deactivated.\nCannot call AEL function \"%s\"' % self.aelFunctionName) 36 37 isAdsBusy = False 38 try: 39 isAdsBusy = empro.toolkit.rpc.callIsShowingModalOrPopupWidget() 40 except: 41 isAdsBusy = True 42 if isAdsBusy: 43 raise Exception("ADS Schematic or Layout are currently busy. Please close all active (modal) dialogs in these tools and retry.") 44 45 try: 46 empro.toolkit.rpc.callAELNonBlocking(self.aelFunctionName, [self.datasetNames, self.failedAnalyses, self.totalSimTime, self.timeOuts, self.pprFileNames, self.schemGenResults]) 47 except: 48 raise

49

50 - def _getLogFileName(self):

51 import os 52 workspaceDir = os.path.join(empro.activeProject.rootDir, os.pardir, os.pardir) 53 logFileName = os.path.join(workspaceDir, "sipiSetupLog.txt") 54 return logFileName

55

56 - def _writePPR2File(self, setup, sim):

57 if sim.engine()!="PPR": 58 return 59 results = self._readEigenFrequenciesFromSim(sim) 60 import os.path 61 import pickle 62 workspaceDir = os.path.join(empro.activeProject.rootDir, os.pardir, os.pardir) 63 64 oaLayout = empro.activeProject.geometry()[0] 65 cellName = oaLayout._designRef.cell 66 67 fileName = "%s_PPR_%s_ppr_results.txt" % (cellName, setup.name.replace(" ","_")) 68 pprFileName = os.path.join(workspaceDir, fileName) 69 with open(pprFileName, "w") as file: 70 pickle.dump(results, file) 71 return fileName

72

73 - def _waitForSimulation(self):

74 import time 75 simulations = empro.activeProject.simulations() 76 if isinstance(simulations, empro.simulation.Simulation): 77 simulations = [simulations] 78 deadline = None 79 if self.timeout: 80 deadline = time.time() + self.timeout 81 while any(sim.status in ('Queued', 'Running', 'PostProcessing', 'Interrupting', 'Killing') for sim in simulations): 82 time.sleep(.1) 83 empro.gui.processEvents() 84 if deadline and time.time() > deadline: 85 for sim in simulations: 86 if sim.status in ('Queued', 'Running'): 87 sim.kill() 88 empro.toolkit.simulation.wait() 89 raise TimeOutError

90

91 - def _getFreqAndQfactorFromLine(self, line):

92 items = line.split() 93 assert("." in items[0]) 94 assert("Hz" in items[2]) 95 unit = empro.units.unitByAbbreviation(items[2]) 96 frequency = unit.toReferenceUnits(float(items[1])) 97 Qfactor = float(items[3]) 98 return (frequency, Qfactor)

99

100 - def _readEigenFrequenciesFromSim(self, sim):

101 if sim.engine()!="PPR": 102 return [] 103 output = sim.output(0) 104 lines = output.splitlines() 105 line = "" 106 while (not "Eigenfrequency" in line and lines): 107 line = lines.pop(0) 108 return [ self._getFreqAndQfactorFromLine(line) for line in lines if "Hz" in line ]

109

110 - def generateSchematic_and_compare(self, logFile, setup, schematicType, whereToSave=0):

111 import time 112 import empro.toolkit.analysis as sipi 113 import empro.toolkit.analysis.schematic_generation as schematic_generation 114 import sys 115 116 overWrite = 1 117 refereceDesignName=None 118 generatedDesignName=None 119 oaLayout = empro.activeProject.geometry()[0] 120 libName = oaLayout._designRef.lib 121 cellName = oaLayout._designRef.cell 122 123 #step1. Rename reference data 124 schematicTypeName = ["", "Sub Circuit", "Test Bench"][schematicType] 125 delim=';' 126 try: 127 refereceDesignName = schematic_generation.renameReferenceCellViewForCompare(libName, cellName, setup, schematicType, whereToSave) 128 except: 129 self.schemGenResults.append("SKIPPED"+delim+setup.name+delim+schematicTypeName+delim+"No reference Schematic found") 130 return generatedDesignName 131 132 #step2. Schem generation 133 try: 134 if schematicType==1: 135 generatedDesignName = sipi.generateSubCircuit(setup, overWrite, noErrorMessageBox=True, whereToSave=whereToSave) 136 elif schematicType==2: 137 generatedDesignName = sipi.generateTestBench(setup, overWrite, noErrorMessageBox=True) 138 except: 139 msg = str(sys.exc_info()[1]) 140 self.schemGenResults.append("FAILED"+delim+setup.name+delim+schematicTypeName+delim+"Schematic generation failed "+msg) 141 return generatedDesignName 142 143 #step3. Compare schematic 144 try: 145 if refereceDesignName and generatedDesignName: 146 result = schematic_generation.compareSchematic(refereceDesignName, generatedDesignName) 147 if result[0]: 148 self.schemGenResults.append("OK"+delim+setup.name+delim+schematicTypeName+delim+result[2]) 149 return generatedDesignName 150 else: 151 self.schemGenResults.append("FAILED"+delim+setup.name+delim+schematicTypeName+delim+"Schematic are different:"+result[2]) 152 return generatedDesignName 153 else: 154 raise 155 except: 156 msg = str(sys.exc_info()[1]) 157 self.schemGenResults.append("FAILED"+delim+setup.name+delim+schematicTypeName+delim+"Failed to compare schematics:"+msg) 158 return generatedDesignName 159 return generatedDesignName

160

161 - def generateSchematic(self, logFile, setup):

162 import time 163 import empro.toolkit.analysis as sipi 164 import empro.toolkit.analysis.schematic_generation as schematic_generation 165 import sys 166 167 overWrite = 1 168 try: 169 designName = sipi.generateTestBench(setup, overWrite, noErrorMessageBox=True) 170 logFile.write("Generate TestBench %s\n" % (designName or "Failed")) 171 return designName 172 except: 173 msg = str(sys.exc_info()[1]) 174 logFile.write("Generate Test Bench Failed\n\t%s\n" % (msg))

175 176

177 - def runCircuitSimulation(self, designName, logFile):

178 import time 179 import empro.toolkit.analysis as sipi 180 import sys 181 try: 182 overWrite = 1 183 closeDesign = 1 184 datasetName = sipi.simulateTestBench(designName, overWrite, closeDesign, noErrorMessageBox=True) 185 logFile.write("Simulate TestBench %s\n" % (datasetName or "Failed")) 186 except: 187 msg = str(sys.exc_info()[1]) 188 logFile.write("Simulate TestBench Failed\n\t%s\n" % (msg)) 189 return 190 if datasetName and len(datasetName) > 0: 191 self.datasetNames.append(datasetName)

192

193 - def runAnalysis(self, logFile, setup):

194 import time 195 import empro.toolkit.analysis as sipi 196 import sys 197 self.failedAnalyses.append(setup.name) 198 logFile.write("\nAnalysis '%s'\n" % setup.name) 199 if (not setup.isValid() and self.mode != 3): 200 logFile.write("Invalid setup\n") 201 return 202 203 if self.mode in [0,1,2]: 204 startTime = time.time() 205 sipi.runAnalysis(setup, waitForConfirmation=False) 206 try: 207 self._waitForSimulation() 208 except TimeOutError: 209 logFile.write("Simulation TimeOut after %s s\n" % self.timeout) 210 self.timeOuts.append(setup.name) 211 self.totalSimTime += self.timeout 212 self.failedAnalyses.pop() 213 return 214 215 endTime = time.time() 216 simTime = endTime - startTime 217 self.totalSimTime += simTime 218 219 lastSim = empro.activeProject.simulations()[-1] 220 logFile.write("Simulation %s\n" % lastSim.status) 221 logFile.write("Simulation Time %s s\n" % simTime) 222 if (lastSim.status == "Error"): 223 logFile.write(lastSim.output(None)) 224 return 225 elif (lastSim.status != "Completed"): 226 raise Exception("Last simulation status is %s" % lastSim.status) 227 228 if lastSim.engine()=="PPR": 229 pprFileName = self._writePPR2File(setup, lastSim) 230 self.pprFileNames.append(pprFileName) 231 self.failedAnalyses.pop() 232 return 233 if self.mode in [1,2]: 234 designName = self.generateSchematic(logFile, setup) 235 if not designName: 236 return 237 if designName and (self.mode in [2]): 238 self.runCircuitSimulation(designName, logFile) 239 elif self.mode == 3: 240 self.generateSchematic_and_compare(logFile, setup, 1) 241 self.generateSchematic_and_compare(logFile, setup, 2) 242 if setup.analysisType in [empro.analysis.Analysis.EMFUAnalysisType, empro.analysis.Analysis.EMFUPEAnalysisType]: 243 self.generateSchematic_and_compare(logFile, setup, 1, 2) 244 self.failedAnalyses.pop()

245

246 - def runAnalyses(self):

247 import empro.toolkit.simulation 248 249 setups = empro.activeProject.analyses 250 empro.activeProject.saveActiveProject() 251 logFileName = self._getLogFileName() 252 with open(logFileName,"a") as logFile: 253 logFile.write("\n=========\nsipiSetup: %s\n=========\n" % empro.activeProject.rootDir) 254 if self.timeout: 255 logFile.write(" timeout = %s s\n" % self.timeout) 256 for setup in setups: 257 self.runAnalysis(logFile, setup) 258 logFile.write("\n")

259

260 - def runAnalysesAndCallAel(self):

261 self.runAnalyses() 262 self.callAel()

Source Code for Module empro.toolkit.analysis.regression_tester